1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a high speed level shifter with a dynamic bias technique under overstress supply voltage.
2. Description of the Prior Art
With the advancement of semiconductor technology, the semiconductor devices become smaller and thinner. In the advanced process, the small transistors can only tolerate a low supply voltage, while the system power supply still remains at a higher level according to specification. For example, if a 1.5V double-data-rate type three (DDR3) memory system is operated in a process having 1.0V core devices and 1.8V I/O devices. The 1.0V core devices cannot be operated in 1.5V due to electrical overstress, which may reduce the robustness and reliability of the devices. The 1.8V I/O devices are not adaptive to 1.5V power supply since the insufficient supply voltage reduces the operating speed of the devices.
The problem is unavoidable since the operating voltage of the peripheral devices does not follow the reduction of tolerance voltage of the transistors in the advanced process. Presently, the transistors may be operated under 1V supply voltage, while the voltage supplied by a battery may be 3.3V. This tremendous voltage difference causes electrical overstress. Thus, there is a need to provide a circuit design to solve the overstress problem.